Certain integrated circuit devices, such as devices utilized in integrated non-volatile memory technology, utilize voltages that can be higher than voltages utilized by logic devices or by volatile memory devices. These integrated circuit devices can utilize metal oxide semiconductor (MOS) field effect transistors to switch voltages on the order of 9-14 volts in order to support programming or erase operations of the integrated non-volatile memory. As device dimensions shrink, there is a corresponding decrease in dimensions of the various components of the device. As an example, a gate oxide thickness of the device can be reduced. As another example, a junction depth of the device can be reduced. As yet another example, a drain depth of the device can be reduced.
These changes in device dimensions can produce manufacturing or operational challenges. As an example, gate induced drain leakage (GIDL) can increase between a body of the device and a drain of the device. This increase in GIDL can increase power consumption of the device or heat generation by the device and can be undesirable.
The increase in GIDL can be addressed by a corresponding increase in gate oxide thickness or by utilizing an extended drain. However, each of these approaches increases the area required by the device and can degrade device performance.